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L9524C
Glow plug system control IC
Features
Quad gate driver for external N-channel Power MOSFETs in high-side configuration: - Gates driven by PWM output signal - Adjustable gate charge/discharge currents - Limited gate-to-source voltages - Negative clamping for inductive loads - Advanced run-off control - Regulation of the power through the glow plugs Control output for external relay driver Battery-voltage-compatible two-wire interface Supply voltage monitoring with shutdown Battery voltage monitoring with shutdown Junction temperature monitoring with shutdown Monitoring of currents through the glow plugs with shutdown at overcurrent (adjustable threshold) Monitoring of external switches Charge pump voltage monitoring with shutdown Active clamping during load dump Device summary
Order code L9524C L9524C-TR Package SO24 SO24
SO24

Description
The L9524C is a control IC for up to six glow plugs of diesel engines. The glow plugs are switched by up to four external PWM-controlled N-channel Power MOSFETs or a single relay in high-side configuration. Supply voltage, battery voltage, junction temperature, switches, currents through the glow plugs, and charge pump voltage are monitored. A two-wire interface is used to communicate with the diesel engine management system.

Table 1.
Packing Tube Tape and reel
January 2008
Rev 3
1/27
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Contents
L9524C
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Control input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switch monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Relay output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gate charge/discharge current variation . . . . . . . . . . . . . . . . . . . . . . . . . 19 Overcurrent threshold variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 6 7
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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L9524C
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Go / no-go protocol description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Failure register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sense input pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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List of figures
L9524C
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Shunt sense versus transistor sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Control input signal in transistor mode (modes 3 to 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Permanent switch on of glow plugs at first falling edge in transistor mode (modes 3 to 6) 14 Control input signal in mode 2 for permanent switch on . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing diagram of advanced run-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mode 1: relay mode, go/no-go diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Mode 2: relay mode, serial diagnostic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode 3: transistor mode, shunt sense, no power regulation . . . . . . . . . . . . . . . . . . . . . . . 23 Mode 4: transistor mode, shunt sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Mode 5: transistor mode, transistor sense, no power regulation . . . . . . . . . . . . . . . . . . . . 24 Mode 6: transistor mode, transistor sense, power regulation . . . . . . . . . . . . . . . . . . . . . . . 24 SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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L9524C
Block diagram
1
Figure 1.
Block diagram
Block diagram
VS GND Supply voltage monitor Thermal shutdown Failure monitor DO Diagnostic output Diagnostic logic Channel 1 Charge pump
CP
Gate driver
G1
SP1 SN1
CI
Control input
Gate driver
G2 SP2 SN2
Reference oscillator
Control logic
Failure monitor Channel 2
SN5
BAT
Voltage controlled oscillator
Channel 3 (same as channel 1)
G3 SP3 SN3 G4
Channel 4
Charge/discharge current
MS CUR OCT
(same as channel 2) Program
Overcurrent threshold
SP4 SN4 SN6 IO
Mode input / relay output
5/27
Pins description
L9524C
2
Pins description
Figure 2. Pin connection (top view)
SP1 G1 SN1 SP2 G2 SN5 SN2 BAT DO VS CP OCT 1 2 3 4 5 6 7 8 9 10 11 12
SO24
24 23 22 21 20 19 18 17 16 15 14 13
SP3 G3 SN3 SP4 G4 SN6 SN4 CI GND MS CUR IO
Table 2.
Pins # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pins description
Name SP1 G1 SN1 SP2 G2 SN5 SN2 BAT DO VS CP OCT IO CUR MS GND CI SN4 SN6 G4 SP4 SN3 G3 SP3 Positive sense input, glow plug 1 Driver output for external high-side power MOSFET, transistor 1 Negative sense input, glow plug 1 Positive sense input, glow plugs 2 and 5 Driver output for external high-side power MOSFET, transistor 2 Negative sense input, glow plug 5 Negative sense input, glow plug 2 Battery voltage input Diagnostic output Supply voltage input Charge pump output Overcurrent threshold setting Transistor mode: input for selection of power regulation feature Relay mode: output to control external relay driver Power MOSFET gate charge/discharge current setting Mode selection input: transistor modes (transistor sense / shunt sense) / relay mode Ground pin Control input Negative sense input, glow plug 4 Negative sense input, glow plug 6 Driver output for external high-side power MOSFET, transistor 4 Positive sense input, glow plugs 4 and 6 Negative sense input, glow plug 3 Driver output for external high-side power MOSFET, transistor 3 Positive sense input, glow plug 3 Function
6/27
L9524C
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol VVS |dVVS/dt| VCP VBAT, VCI, VSP1-4, VSN1-6
Absolute maximum ratings
Parameter Supply voltage range Supply voltage slope Charge pump voltage range Input pin voltage range (BAT, CI, SP1-4, SN1-6) Value -0.3 to 45 10 -0.3 to 45 -16 to 45 Unit V V/s V V
VOCT, VCUR, Input pin voltage range (OCT, CUR, MS, IO) VMS, VIO VDO, VG1-4 Output pin voltage range (DO, G1-4)
-0.3 to 7 -16 to 45
V V
Warning:
The device may become damaged if using externally applied voltages or currents exceeding these limits!
All the pin of the IC are protected against ESD. the verification is performed according to: AEC Q100-002 (HBM) and AEC Q100-011 (CDM).
3.2
Thermal data
Table 4.
Symbol TJ TJSD
Thermal data
Parameter Operating junction temperature Junction temperature thermal shutdown threshold Value -40 to 125 125 to 150 Unit C C
7/27
Electrical specifications
L9524C
3.3
Electrical characteristics
5V VVS;VBAT 18V, -40C TJ 125C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when current flows into the pin.
Table 5.
Item
Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply (VS) 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 IVS VVS uv VVS uvh VVS ol VVS ov VVS ovh VVS ld tVS fil tVS ld Supply current VS = 12V Undervoltage threshold Undervoltage threshold hysteresis (1) Open-load detection threshold Overvoltage threshold Overvoltage threshold hysteresis (1) Load dump threshold Filter time (2) Load dump delay time
(1)
5
20 10 5 400 7.2 22 1.6 35 2
mA mA V mV V V V V ms s
1 4 100 5.5 18 0.4 28 1 10
Supply (BAT) 2.1 IBAT leak Leakage current VVS 3V 0V VBAT 12V -40C 2.2 RBAT Internal pull-down resistance Battery undervoltage threshold Filter time (2) 30C 125C 2.3 2.4 VBAT uv tBAT fil VMS > VMS tr (transistor mode) 0 25 25 25 1 300 43 65 106 5 150 150 150 2 760 V s k A
Charge pump (CP) 3.1 3.2 3.3 3.4 3.5 VCP ICP VCP uv fCP tCP fil Charge pump voltage Charging current Charge pump undervoltage threshold Charge pump frequency
(1)
ICP = -100A VCP = VVS + 5V
VVS +5V -1500 VVS +3.5V 0.6 400
VVS +18V -100 VVS +5V 7 950 MHz s A
Filter time (2)
8/27
L9524C Table 5.
Item
Electrical specifications Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Control input (CI) 4.1 4.2 4.3 4.4 VCI off VCI on VCI h VCI to Input "off" level Input "on" level Off-to-on hysteresis (1) Input "timeout" threshold VCI VVS; -40C 4.5 RCI Internal pull-up resistance Filter time
(2) (2)
0.6 * VVS 0.4 * VVS 0.03 * VVS 1 20 20 20 0.5 50 35 53 87 0.04 * VVS 0.05 * VVS 1.6 120 120 120 1 100 ms ms k V
VCI VVS; 30C VCI VVS; 125C
4.6 4.7
tCI fil tCI to
PWM time-out
Diagnostic output (DO) 5.1 VDOL Output low voltage Internal pull-up resistance Current limitation VVS 4.5V; IDO 5mA VDO VVS; -40C 5.2 RDO VDO VVS; 30C VDO VVS; 125C 5.3 IDO max 0.3 20 20 20 5 30 45 74 1.5 120 120 120 20 mA k V
Monitoring of currents through glow plugs (SP1-SN1, SP2-SN2, SP3-SN3, SP4-SN4, SP2-SN5, SP4-SN6) 6.1 VOL Open-load threshold 6V VSPX;VSNX VVS + 3V 1.5V VSPX;VSNX VVS + 3V VMS < VMS tc (shunt sense) OCT pin open 1.5V VSPX;VSNX VVS + 3V VMS < VMS tc (shunt sense) 0V VOCT VCUR 1.5V VSPX;VSNX VVS + 3V VMS>VMS tc (transistor sense) = -40C; OCT pin open 1.5V VSPX;VSNX VVS + 3V VMS>VMS tc (transistor sense) = -40C; 0V VOCT VCUR 6.3 TCOC tOL fil Overcurrent threshold temperature coefficient Open-load filter time (2) VMS < VMS tc (shunt sense) 1) VMS>VMS tc (transistor sense) OCT pin open VMS > VMS tr (transistor mode) 0.008 1 6.7 150 14.7 185 mV mV
VOCT * 0.385
VOCT * 0.445
6.2
VOC 0
Overcurrent threshold
150
290
mV
VOCT * 0.345 0
VOCT * 0.485 K-1 0.012 2 K-1 ms
6.4
9/27
Electrical specifications Table 5.
Item 6.5
L9524C
Electrical characteristics (continued)
Symbol tOC fil Parameter Overcurrent filter time
(2)
Test condition
Min. 400
Typ.
Max. 950
Unit s
Monitoring of external switches (SN1, SN2, SN3, SN4) 7.1 7.2 VSD tSD fil Switch defect threshold Switch defect filter time
(2)
VVS * 0.4 1
VVS * 0.6 2 ms
Gate driver outputs (G1, G2, G3, G4) 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 VG off VG on VG cl IG off IG on Slope RG tG on Gate off voltage Gate on voltage Gate clamping voltage Gate discharge current Gate charge current Gate charge- dischargecurrent IG/ICUR Output resistance (1) Jitter of output on time -300 IGX 100A VSNX = VVS VSNX = -20V ICUR = -125A ICUR = -125A -250A ICUR -70A VSNX VVS +5V -18 270 270 2.33 1 300 VSNX +0.7V VVS +10V -16 540 540 4.33 k s V A A
Mode input / relay output (IO) 9.1 9.2 9.3 9.4 9.5 9.6 VIO on RIO IIO IIO max VIO pr tIO sup Output on voltage Output resistance Input pull-down current Current limitation Power regulation threshold Pulse suppress time (2) IIO -100A IIO -1mA VIO 1V VVS = 0V 3 100 25 50 -25 1 2.5 6 500 100 500 -5 2 5 V W A A mA V ms
Positive sense inputs (SP1, SP2, SP3, SP4) 10.1 10.2 ISP leak ISP Leakage current Input pull-down current VVS 3V VSNX = VSPX 6V 6V VSNX = VSPX 20V -40C 10.3 RSP1-4 Pull-down resistor 35C 125C Negative sense inputs (SN1, SN2, SN3, SN4, SN5, SN6) 11.1 ISN Input pull-down current VSNX = VSPX 6V 15 780 A 0 15 40 40 40 100 150 220 5 780 270 270 270 k A A
10/27
L9524C Table 5.
Item
Electrical specifications Electrical characteristics (continued)
Symbol Parameter Test condition 6V VSNX = VSPX 20V -40C Min. 40 40 40 Typ. 100 150 220 Max. 270 270 270 k Unit
11.2
RSN1-6
Pull down resistor
35C 125C
Overcurrent threshold setting (OCT) 12.1 IOCT Input pull-up current VVS 6V VOCT = 3.5V -40 -10 A
Power MOSFET gate charge/discharge current setting (CUR) 13.1 13.2 VCUR ICUR max Output voltage Current limitation ICUR -150A VCUR 2V 2.35 -500 2.5 2.65 -250 V A
Input pin for mode selection (MS) 14.1 14.2 14.3 IMS VMS tr VMS tc Pull-up current Transistor mode threshold Temperature compensation threshold VVS 6V VMS = 3V -60 1 3 -15 2 4 A V V
Output timing 15.1 15.2 15.3 tdel tgap tsup Delay time (2) Gap between channels
(2)
2.5 50 400
5 250 950
ms s s
Failure suppress time (2)
Power regulation 8V VBAT 16V 30ms TCI 33ms tCI on/TCI 20% < 70C > 70C
1. not tested, guaranteed by design 2. time constants created digitally, verified by scan path test
16.1
VRMS
-1.5
1.5%
Accuracy
%* VRMSref
-2
2
11/27
Functional description
L9524C
4
4.1
Functional description
Operating modes
The L9524C can operate in a total of 6 modes. The selection is done by short-circuiting the appropriate pins and voltages as shown in the following table:
Table 6.
Mode 1 2 3 4 5 6
Mode
Description relay mode, go/no-go diagnostic interface protocol relay mode, serial diagnostic interface protocol transistor mode, shunt sense, no power regulation transistor mode, shunt sense, power regulation transistor mode, transistor sense, no power regulation transistor mode, transistor sense, power regulation MS pin ground ground CUR pin CUR pin open open BAT pin ground battery battery battery battery battery IO pin output output CUR pin ground CUR pin ground CI pin statical signal PWM signal PWM signal PWM signal PWM signal PWM signal
Modes 1 and 2 are for relay usage (referred to as "relay mode") and modes 3 to 6 for transistors usage (referred to as "transistor mode"). In relay mode the protocol of the diagnostic interface (DO pin) can be selected from go/nogo protocol and serial protocol (see section "Diagnostic output" for protocol description). In transistor mode the protocol of the diagnostic interface is the serial protocol. It can be distinguished between using shunts for monitoring the current through the glow plugs (referred to as "shunt sense") or using the RDS(on) of the power MOSFET's themselves (referred to as "transistor sense"). In shunt sense mode the resistance of the shunt is assumed to be constant with respect to the temperature while in transistor sense mode the RDS(on) of the power MOSFET's is assumed to vary with respect to the temperature and therefore overcurrent monitoring is adjusted appropriately. In transistor mode there are two possibilities to control the output timing. In modes 3 and 5 the timing of the PWM control input signal determines the timing of the PWM signals applied to the external power MOSFET's ("no power regulation"). In modes 4 and 6 the timing of the PWM control input signal determines the power through the glow plugs ("power regulation") and the timing of the PWM signals applied to the external power MOSFET's is adjusted depending on the battery voltage (see section "Power regulation").
12/27
L9524C Figure 3. Shunt sense versus transistor sense
shunt sense VBAT transistor sense
Functional description
VBAT
SPx Gx
L9524C
SPx shunt SNx glow plug
L9524C
Gx
SNx glow plug
015
4.2
Supply
The main supply pin of the L9524C is the VS pin. The voltage applied to it (VVS) is monitored

to switch off all glow plugs if it is less than VVS uv for at least tVS fil ("under voltage failure"), to switch off all glow plugs if it is greater than VVS ov for at least tVS fil ("over voltage failure"), to switch on all glow plugs if it is greater than VVS ld for at least tVS ld ("active clamping during load dump"), to ignore open-load failures if it is less than VVS ol.
Note:
The glow plugs are switched on again if the corresponding switch-on condition disappears, except if the glow plugs are switched on because of load dump. Then they remain switched on until VVS is less than VVS ov for at least tVS fil. In modes 2 to 6, the L9524C is additionally supplied by the BAT pin. This auxiliary supply ensures that the external power MOSFET's are switched off if no main supply voltage is available at the VS pin. The BAT pin is additionally used to sense the battery voltage VBAT for power regulation in modes 4 and 6 (see section "Power regulation") and for detecting "battery under voltage failure" (fuse between battery and module is defect) if VBAT is less than VBAT uv for at least tBAT fil in modes 2 to 6. An additional supply voltage higher than the main supply voltage is generated by an internal charge pump which charges an external storage capacitor connected to the CP pin. This capacitor mainly supplies the gates of the external n-channel power MOSFET's. The charge pump voltage VCP is monitored and the glow plugs are switched off if it is less than VCP uv for at least tCP fil ("charge pump under voltage"). Afterwards, the glow plugs remain switched off even if the charge pump voltage becomes greater than VCP uv until they are explicitly switched on again by the CI (control input) pin.
13/27
Functional description
L9524C
4.3
Control input
The control input (CI) pin is resistively pulled up RCI to the supply voltage VVS such that VCI=VCI off and the glow plugs are switched off by default. The L9524C is controlled by transitions of VCI from VCI off to VCI on (falling edge) and vice versa (rising edge). Voltage level changes of VCI which last shorter than tCI fil are ignored. In transistor mode (modes 3 to 6) the L9524C expects a PWM signal at the CI pin. Each falling edge starts measuring its on time tCI on (time until next rising edge, i.e. length of this low pulse) and its period TCI (time until next falling edge). The end of a pulse group is detected if no falling edge occurs for a time greater than tCI to and the glow plugs are switched off. Therefore, it is not possible to switch on the glow plugs permanently with one exception: if the low voltage level of the first falling edge is greater than VCI to the glow plugs remain switched on as long as this low pulse lasts. Figure 4.
VCI VCI off 0.6 . V VS 0.4 . V VS VCI on glow plug 1 ON OFF t tCI on tCI fil +t del
Control input signal in transistor mode (modes 3 to 6)
tCI to TCI tCI fil ignored (shorter than tCI fil ) tCI fil
tCI to tCI fil +t del
tCI to
t
Figure 5.
Permanent switch on of glow plugs at first falling edge in transistor mode (modes 3 to 6)
VCI VCI off 0.6 . VVS 0.4 . VVS VCI on VCI to glow plug 1 ON OFF
tCI to
tCI to
tCI to
tCI to
t
t
14/27
L9524C
Functional description Though in mode 2 (relay mode, serial diagnostic interface protocol) the relay should be switched permanently the L9524C also expects a PWM signal at the CI pin since the serial diagnostic interface protocol is synchronized by falling edges of the CI signal (see section "Diagnostic output"). The relay then is switched on permanently if the off time (time between rising and falling edge) of the PWM signal is less than tIO sup since the relay output suppresses pulses shorter than tIO sup (see section "Relay output"). For the same reason the relay is switched off permanently if the on time (time between falling and rising edge) of the PWM signal is less than tIO sup. In all other cases the relay is switched according to the PWM signal at the CI pin. Figure 6. Control input signal in mode 2 for permanent switch on
VCI VCI off 0.6 . V VS 0.4 . V VS VCI on relay ON OFF
TCI
tIO sup
tIO sup
tCI fil +tdel
t
t
In mode 1 (relay mode, go/no-go diagnostic interface protocol) no edges are necessary for the go/no-go protocol. Therefore the relay is switched on if VCI = VCI on and it is switched off if VCI = VCI off.
4.4
Diagnostic output
The diagnostic output stage of the L9524C (DO pin) consists of a current-limited low-side switch and a pull-up resistor RDO to the VS pin. The voltage level of a logical low signal VDOL is given by the drop across the low-side switch and the voltage level of a logical high signal is equal to VVS. The L9524C is able to detect the following failures (see sections "Supply", "Current monitoring", and "Switch monitoring"):

open-load (6 glow plugs), overcurrent (6 glow plugs, stored until power-down), any switch is defect (4 switches), supply voltage (VVS) is too low ("under voltage"), supply voltage (VVS) is too high ("over voltage"), junction temperature (TJ) is too high, charge pump voltage (VCP) is too low ("charge pump under voltage"), and battery voltage (VBAT) is too low ("battery under voltage").
15/27
Functional description
L9524C
In order to report the occurrence of any of the above-listed failures to the diesel engine management system the L9524C provides two protocols: go/no-go protocol for mode 1 and serial protocol for modes 2 to 6. The go/no-go protocol is only able to report if any of the above-listed failures occurred. This is done according to the following table: Table 7.
VCI VCI off VCI on
Go / no-go protocol description
VDO at "no failure" VDOL VVS VDO at "any failure" VVS VDOL
Note:
overcurrent failures are stored until power-down. The serial protocol is able to report different kinds of failures and to assign them to the corresponding glow plugs. Therefore, occurring failures are written into an internal 8-bit failure register: Table 8.
Bit 1 2 3 4 5 6 7 Open-load or overcurrent
(1)
Failure register description
Meaning of high state failure at glow plug 1
Open-load or overcurrent (1) failure at glow plug 2 Open-load or overcurrent (1) failure at glow plug 3 Open-load or overcurrent (1) failure at glow plug 4 Open-load or overcurrent (1) failure at glow plug 5 Open-load or overcurrent (1) failure at glow plug 6 Overcurrent failure at any glow plug (1) or battery voltage (VBAT) is too low (2) ("battery undervoltage") One or more of the following failures ("module failure"): any switch is defect supply voltage (VVS) is too low ("undervoltage") supply voltage (VVS) is too high ("overvoltage") junction temperature (TJ) is too high charge pump voltage (VCP) is too low ("charge pump undervoltage") battery voltage (VBAT) is too low (2) ("battery under voltage")
8
1. overcurrent failures are stored until power-down 2. if battery voltage is too low ("battery under voltage") bits 7 and 8 are high
Bits 1 to 6 are assigned to the glow plugs. Depending on bit 7 they show open-load (bit 7 is low) or overcurrent failures (bit 7 is high). Bit 8 shows if there is any of the listed failures ("module failure"). In case of a battery under voltage failure bits 7 and 8 are high and all other bits are low as long as there is no overcurrent failure stored. For transmitting the contents of the failure register the PWM signal applied to the CI pin is used as clock input: at any falling edge of the CI signal (see section "Control input") the DO pin shows the value of the next bit of the bit stream after tDO del.
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L9524C
Functional description Each transmission frame consists of a beginning delimiter (one low bit) followed by the 8 bits of the failure register beginning with bit 1. After the ending delimiter (one high bit) the diagnostic output stage is inactive and is resistively pulled up to VVS. The L9524C starts transmitting the first frame at the very first falling edge of the CI signal after power-on. Since at that time the contents of the failure register are clear the first 9 bits (beginning delimiter followed by the contents of the 8-bit failure register) which are transmitted are always low. The L9524C repeats transmission of the frame every 32 falling edges of the CI signal. Only during the time when the diagnostic output stage is inactive (i.e. between the transmission of two frames) the contents of the failure register can be written. Figure 7.
VVS ... t 1 2 3 4 5 6 7 8 9 10 ... t
Serial diagnostic interface protocol
VCI VCI off VCI on VDO
0
1
2
3
4
5
6
7
8
9 10 11
... 31 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
high
high
VVS
low
VDOL
beginning delimiter
beginning delimiter
ending delimiter
low
... t
contents of failure register (all bits='low' at 1st frame) first frame
diagnostic output stage inactive
contents of failure register
frame
4.5
Current monitoring
The L9524C is able to monitor the current through 6 glow plugs by measuring the voltage drop across sense resistors. Therefore, there are 4 positive sense input pins (SP1, SP2, SP3, SP4) and 6 negative sense input pins (SN1, SN2, SN3, SN4, SN5, SN6). The sense input pins must be connected to the sense resistors according to the following table: Table 9. Sense input pin connection
Positive sense input pin SP1 SP2 SP3 SP4 SP2 SP4 Negative sense input pin SN1 SN2 SN3 SN4 SN5 SN6
Sense resistor of glow plug 1 2 3 4 5 6
ending delimiter
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Functional description
L9524C
In relay mode (modes 1 and 2) the positive sense input pins are short-circuited since the relay is the only switch. In transistor mode (modes 3 to 6) glow plug 5 is switched with transistor 2 and glow plug 6 with transistor 4. Therefore only 4 positive sense input pins are necessary. If the voltage drop across the sense resistor is less than VOL for at least tOL fil an open-load failure is detected as long as VVS > VVS ol. If it is greater than VOC (see below for definition) for at least tOC fil an overcurrent failure is detected and the corresponding switch is switched off and remains switched off until power-down. The threshold for overcurrent failures VOC can be varied by the voltage applied to the OCT pin (see section "Overcurrent threshold variation"). In modes 1 to 4 the overcurrent threshold is constant with respect to the temperature (TCOC = 0). But in modes 5 and 6 the overcurrent threshold increases linearly with the temperature to compensate the first-order temperature coefficient of the RDS(on) of the external power MOSFET's which are used as sense resistors in these modes: Equation 1 VOC = VOC 0 (1 + TCOC ( + 40C)).
4.6
Switch monitoring
The L9524C monitors the voltages across the glow plugs (using the negative sense input pins SN1, SN2, SN3, and SN4) to detect if the corresponding switches work properly or not. A switch is detected as defect if it is switched on but the voltage across the corresponding glow plug(s) is less than VSD for at least tSD fil or if it is switched off but the voltage across the glow plug(s) is greater than VSD for at least tSD fil.
4.7
Thermal shutdown
If the junction temperature becomes greater than TJSD all glow plugs are switched off. They are switched on again if the junction temperature falls below TJSD.
4.8
Gate drivers
The L9524C contains four gate drivers (Gx pins) for external n-channel power MOSFET's in high-side configuration. Each gate driver provides a slope control by charging and discharging the gates of the external power MOSFET's with constant currents (IG on or IG off). To adjust the slopes these currents can be varied using the CUR pin (see section "Gate charge/discharge current variation"). The charging current source is supplied by an external capacitor connected to the charge pump output (CP) pin. The gate-to-source voltages are limited internally and without supply voltage (VVS) the gates and the sources of the external power MOSFET's are short-circuited. During free-wheeling of inductive loads the gates of the external power MOSFET's are clamped to VG cl. As a result, the power MOSFET's become conducting and the energy in the inductive loads is recirculated through the power MOSFET's.
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L9524C
Functional description
4.9
Relay output
In relay mode (modes 1 and 2) the IO pin is used as output pin to control an external relay driver (e.g. a low-side switch which drives the relay). If the output stage of the IO pin is switched on it behaves like a voltage source (VIO) with output resistance RIO. If it is switched off a pull-down current source is activated (IIO). The relay output suppresses pulses shorter than tIO sup such that the relay can be permanently switched by applying appropriate PWM signals to the CI pin (see section "Control input"). In transistor mode (modes 3 to 6) the IO pin is used as input pin. Left open it is pulled down to ground and the power regulation feature (see section "Power regulation") is activated (VIO < VIO pr). To deactivate the power regulation feature the IO pin must be connected to the CUR pin (VIO = VCUR > VIO pr).
4.10
Gate charge/discharge current variation
The CUR pin provides a constant current-limited output voltage VCUR. The gate charge (or discharge) current is a multiple of the current flowing out of the CUR pin and can therefore be varied by applying a resistor to the CUR pin. In order to select the mode of operation the IO pin and/or the MS pin may be connected to the CUR pin (see section "Modes"). The IO pin contains a pull-down current source and the MS pin contains a pull-up current source. These currents are compensated if the corresponding pin is connected to the CUR pin in order not to affect the gate charge/discharge current.
4.11
Overcurrent threshold variation
The overcurrent threshold VOC can be varied by connecting the OCT pin to an external resistive voltage divider between CUR pin and ground. If the OCT pin is left open it is pulled up to an internal supply voltage by a current source and a default value is used for the overcurrent threshold. This default value corresponds to the condition: VOCT = VCUR/6. In order not to de tune the voltage divider the pull-up current IOCT source is deactivated when any glow plug is switched on.
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Functional description
L9524C
4.12
Advanced run-off control
In transistor mode (modes 3 to 6) the glow plugs are switched by an advanced run-off control. The target is to minimize changes in the load current. Therefore, the PWM signals applied to the glow plugs are phase-shifted to each other. There is a 5-step start-up procedure at the beginning of a switching sequence. In step 1 the phase shift between the glow plugs is set to a fixed value tdel. Therefore, all glow plugs are switched on once in the first period of the PWM control input signal (CI) and are heated up quite simultaneously. During the start-up procedure the phase shift becomes a value equal to the on time of one glow plug. As a result, after the start-up procedure the glow plugs are switched on one after the other to get minimal changes in the load current. Figure 8. Timing diagram of advanced run-off control
4.13
Output timing
In transistor mode (modes 3 to 6) there is a delay tgap between switching off one glow plug and switching on the next one to avoid overlaps. Additionally, failures occurring during the slope (i.e. in the time period tsup after switching) are suppressed in all modes. Figure 9. Output timing
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L9524C
Functional description
4.14
Power regulation
The power through each glow plug (here expressed by VRMS which is the root-mean-square voltage across one glow plug) depends on the battery voltage VBAT and the duty cycle tG on/TG of the PWM signal applied to the external power MOSFET's: Equation 2 t G on V RMS = V BAT -----------TG In order to regulate the power through the glow plugs the L9524C measures VBAT and adjusts tG on/TG of the gate drivers (G1...4) such that VRMS = VRMS ref, where VRMS ref represents the desired power through each glow plug. The desired power VRMS ref is given by the input duty cycle tCI on/TCI which represents the desired output duty cycle at a nominal battery voltage of 12V: Equation 3 t CI on V RMS ref = 12V ------------t CI As a result, the actual output duty cycle of the gate drivers is given by: Equation 4 t G on 12V 2 t CI on ------------ = -------------- ------------V T CI TG BAT
Note:
The L9524C varies both the on time tG on and the period TG of the PWM output signal to vary the duty cycle tG on/TG. The accuracy of the power regulation is given by VRMS = VRMS - VRMS ref. The output jitter (electrical characteristics Item 8.8) is not taken in considuration while the average is zero over some periodes.
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Application diagrams
L9524C
5
Application diagrams
Figure 10. Mode 1: relay mode, go/no-go diagnostic interface protocol
L9524 KL 87 220N Vs BAT CP KL 31 GND G1 G2 G3 10K Control CI Diagnosis 100R DO SN1 SP2 47R SN2 SP3 47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 47R VOCT OCT SN6 Glow plug Rs Rs Rs Rs Rs G4 SP1 47R Rs 470P 220N Vbatt KL 30
KL 31
Figure 11. Mode 2: relay mode, serial diagnostic interface protocol
L9524 KL87 220N Vs BAT CP KL31 GND G1 G2 G3 10K Control CI Diagnosis 100R DO SN1 SP2 47R SN2 SP3 47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 47R VOCT OCT SN6 Glow plug Rs Rs Rs Rs Rs G4 SP1 47R Rs 470P 470P 220N 220R Vbatt KL30
KL31
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L9524C Figure 12. Mode 3: transistor mode, shunt sense, no power regulation
L9524 KL87 220N Vs 470P BAT CP KL31 GND G1 G2 G3 10K Control CI 100R Diagnosis DO 100R SN2 SP3 47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 47R VOCT OCT SN6 Glow plug Rs SN1 SP2 47R Rs G4 SP1 47R Rs 470P 220N 220R STB100NF04 STP85NF55
Application diagrams
STB100NF04 100N Vbatt KL30
STP85NF55
100R
Rs Rs Rs
KL31
Figure 13. Mode 4: transistor mode, shunt sense, power regulation
L9524 KL87 220N Vs CP KL31 GND G1 G2 G3 10K Control CI 100R Diagnosis DO 100R SN2 SP3 47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 47R VOCT OCT SN6 Glow plug Rs Rs Rs Rs SN1 SP2 47R Rs G4 SP1 47R Rs 470P 220N 100R 470P BAT 220R STB100NF04 STP85NF55 STB100NF04 100N Vbatt KL30 STP85NF55
KL31
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Application diagrams Figure 14. Mode 5: transistor mode, transistor sense, no power regulation
L9524 220N Vs 470P BAT 220R STP85NF55 100N Vbatt KL30 100R 220N
L9524C
KL87
CP KL31 GND G1 G2 G3 10K Control CI 100R Diagnosis DO 100R SN2 SP3 SN1 SP2 G4 SP1 470P
47R
47R
47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 VOCT OCT SN6 47R
Glow plug
KL31
Figure 15. Mode 6: transistor mode, transistor sense, power regulation
L9524 220N Vs 470P BAT 220R STP85NF55 100N Vbatt KL30 100R 220N
KL87
CP KL31 GND G1 G2 G3 10K Control CI 100R Diagnosis DO 100R SN2 SP3 SN1 SP2 G4 SP1 470P
47R
47R
47R IO MS ICUR CUR SN3 SP4 47R SN4 SN5 VOCT OCT SN6 47R
Glow plug
KL31
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L9524C
Package information
6
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. SO24 mechanical data and package dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 15.20 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 15.60 7.60 MIN. 0.093 0.004 0.013 0.009 0.598 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.614 0.299 Weight: 0.60gr inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO24
0070769 C
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Revision history
L9524C
7
Revision history
Table 10.
Date 22-Sep-2006 29-Sep-2007
Document revision history
Revision 1 2 Initial release Updated the Section 3.3: Electrical characteristics. Modified the Figure 5 and Figure 7. Added the sub-title Section 4.3: Control input. Modified the values of the items 1.8, 6.4 and 7.2, and the parameter definition of the item 8.6 in the Section 3.3: Electrical characteristics. Description of changes
9-Jan-2008
3
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L9524C
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